The present invention relates in general to digital communication systems and networks, and is particularly directed to a mechanism for enabling a channel bank-installed ISDN channel unit to controllably xe2x80x98spoofxe2x80x99 a channel bank controller to release time slots assigned to a different card slot, and thereby enable the usurping channel unit to conduct 2B+D ISDN communications without the use of a null card.
Integrated services digital network (ISDN) communication networks, such as the xe2x80x98extended distancexe2x80x99 ISDN communication network architecture diagrammatically illustrated in FIG. 1, enable telephone service providers to supply multiple types of signalling channels from a central office to a network termination interface at a customer premises site. In the reduced complexity network example of FIG. 1, a PCM communication link 10, such as a T1 data rate (1.544 Mb/s) optical fiber link, provides digital communication connectivity between a central office (CO) channel bank 20, such as an ATandT SLC series 5 channel bank, at a xe2x80x98westxe2x80x99 end of the PCM link, and customer premises equipment (CPE) served by a channel bank 30 located at a remote, xe2x80x98eastxe2x80x99 end 40 of the link.
The west end central office 20 is coupled by way of a link 21 to a central office switch 22 (such as a 5ESS switch manufactured by ATandT), and includes a line interface unit (LIU) 23 that terminates the west end of the PCM link 10. The east end channel bank 30 has an LIU 33 coupled to the PCM link, and includes a plurality of U-BRITE circuit cards 35 coupled via associated local loops (twisted tip/ring pair) 37 to customer premises equipment (CPE) 40. As shown in FIG. 2, the line interface unit 33 of the east end channel bank 30 is coupled over an internal PCM bus 34 to a plurality of ISDN channel units or U-BRITE circuit cards 35 installed within card slots of the channel bank""s backplane 36. Each respective U-BRITE circuit card 35 is dedicated to providing extended ISDN service to remote customer premises equipment via a local loop 37 that connects the channel unit with digital communication equipment 40 installed at the customer premises.
Under control of a communications control processor or channel bank control unit (BCU) 38, a carrier system transceiver within the line interface unit 33 is operative to transmit and receive standard 2B+D ISDN data traffic over the PCM digital data link 10. In order to interface a digital subscriber loop (DSL) over the local loop (twisted pair) 37 to the customer premises equipment 40, each U-BRITE card 35 includes a line transceiver and an associated line interface, which are also operative under microprocessor control to interface PCM data with the line interface unit 33, and to transmit and receive basic rate 2B1Q ISDN signals over the local loop 37 to and from the customer premises equipment 40.
In some channel banks, the bank controller unit may not be designed to recognize ISDN common cards (ISDN channel units) installed in the channel bank""s backplane. Since ISDN channel units require the use of three time slots (i.e., two bearer (B1 and B2) and one data (D)), and the bank controller assigns only two time slots per backplane card slot, it has been customary practice, as shown at 39 in FIG. 2, to install what is commonly known in the industry as a xe2x80x98nullxe2x80x99 card 39, in a card slot that is immediately adjacent to the card slot containing an ISDN channel unit or U-BRITE card 35.
While containing no transceiver circuitry of its own, the null card is configured to appear to the BCU as a standard POTS card, so that the bank controller unit will release or assign (a pair of) time slots associated with the null card""s backplane card slot. Since the null card does not transmit, these time slots are available for use as third time slots of adjacent U-BRITE cards.
Although installing a null card is one way to induce the bank controller unit to release two otherwise unused time slots for utilization by adjacent ISDN channel cards, it requires that the ISDN service provider purchase and physically install a null card for every two ISDN cards employed.
In accordance with the invention, the above-described cost and labor penalty of having to purchase and install null cards in an ISDN channel bank is effectively obviated by taking advantage of an a priori search sequence that is conducted by the bank controller unit whenever a service request (SR) signal is generated by a channel unit, irrespective of the backplane card slot in which the channel unit sourcing the service request is installed. In particular, it has been observed that the channel bank controller unit will always respond to a service request by polling the card slots for the presence of channel units, beginning with the lowest numbered card slot, and then proceeding sequentially through the remaining (twelve per digroup) card slots of the backplane.
Unfortunately, even with knowledge of the order of the polling sequence, and the fact that each channel unit can read each of the messages being clocked over a common channel unit, there is the problem that the card slot addresses lines (including a selectively clocked enable or xe2x80x9cnot message page (NMP)xe2x80x9d line and an asynchronous clock or xe2x80x9cnot message quadrant (NMQ)xe2x80x9d line) are not common to all channel units. Instead, for each digroup of card slots, the address lines are selectively wired in sets or groups (two NMQ lines for two sets of six card slots each, and six NMP lines respective assigned to non-adjacent pairs of card slots (1/7, 2/8, 3/9, 4/10, 5/11 and 6/12)). As a consequence, each channel unit cannot determine when the bank controller is addressing another (in particular, the adjacent) card slot.
As will be described, this problem is obviated in accordance with the invention, by employing the NMQ clocking signals generated by the bank controller for a given plurality of channel units, of which an ISDN channel unit of interest is a member, to artificially generate a xe2x80x98pseudo NMPxe2x80x99 signal, the duration of which corresponds to a period of time slightly longer than the length of time that the sequence of NMQ signals is being asserted by the bank controller. This combination of NMQ signals on the NMQ lead and the pseudo NMP signal enables the ISDN channel unit of interest to conduct serial message exchanges (read/write operations) with the bank controller during an interrogation interval associated with another (the adjacent) backplane card slot. The bank controller unit is thereby effectively fooled or xe2x80x98spoofedxe2x80x99 into thinking that a channel unit is actually installed in that backplane slot, so that it releases the pair of time slots associated with that adjacent card slot, and thereby allows the ISDN channel unit to usurp one of the two released time slots it needs for its set of three (2B+D) ISDN channels.
For this purpose, upon being installed in the channel bank, the modified ISDN channel unit according to the present invention generates a communication service request (SR) signal. As described above, this communication service request signal will stimulate the channel bank controller to poll each channel unit installed in the channel bank, so that the bank controller may ascertain which circuit card slots actually contain channel units. Such polling of the card slots is conducted by means of the set of selectively clocked NMP and NMQ address lines and an associated common message (MSG) line to which the card slots are connected.
The modified ISDN channel unit of the present invention includes a set of interface logic that is coupled in circuit between the NMP and NMQ input leads and the message exchange circuitry of the channel unit to which the NMP and NMQ leads are normally directly connected. The interface logic has an output gate to an input of which the NMP input lead of the backplane communication bus is coupled. The output of this output gate is coupled to control the state of an NMP output lead to the channel unit""s message exchange circuitry.
Whenever the channel unit sees its NMP lead go low, it changes the state of an enable lead, which is coupled to an input gate, and is maintained in a prescribed logic state for a duration that extends over the length of time that the bank controller polls the card slot of the interrogated channel unit of interest and the immediately adjacent downstream card slot. This input gate is also coupled to the NMQ lead for that channel unit. As long as the enable lead is asserted in this logic state, the output of the input gate will follow the changes in state (clocking) of the NMQ lead by the bank controller.
The output of the input gate is coupled to the clear input of a divide-by-N counter and to the reset input of an output flip-flop. The output flip-flop is clocked by the output of a counter, when the counter rolls over. When enabled, the counter is coupled to count high speed clock pulses. The parameters of the counter are such that it will not reach its rollover count limit prior to the expiration of one period of the NMQ signal on the NMQ lead.
As a long as the NMQ lead is being clocked by the bank controller unit, it will repeatedly reset the counter and the output flip-flop, preventing the counter from rolling over and clocking the output flip-flop to a state that changes the state of the NMP output lead.
However, when the bank controller unit terminates its interrogation of the present card slot, it ceases clocking the NMQ lead, and also changes the state of the NMP input lead. The lack of a transition of the NMQ lead will eventually allow the counter to roll over, so that the counter will clock the output flip-flop, changing the state of the NMP output lead.
Although the channel unit cannot read the state of the adjacent card""s NMP lead, the availability of the NMQ lead it shares with the adjacent card slot enables the channel unit to artificially generate a xe2x80x98pseudo NMPxe2x80x99 signal on its NMP output lead, which has a duration that is slightly longer than the length of time that the sequence of NMQ signals is being asserted by the bank controller. This combination of clocked NMQ signals on the shared NMQ lead and the pseudo NMP signal enables the ISDN channel unit to conduct serial message exchanges with the bank controller during an interrogation interval associated with the adjacent card slot. The bank controller unit is thereby effectively xe2x80x98spoofedxe2x80x99 into thinking that a channel unit is actually installed in that backplane slot, so that it releases the pair of time slots associated with that adjacent card slot, and allows the ISDN channel unit to usurp one of the two released time slots it needs for its set of three (2B+D) ISDN channels.
Eventually, the bank controller unit terminates its interrogation of the adjacent card slot, as it ceases clocking the NMQ lead for that card slot. The lack of a high-to-low transition of the NMQ lead to the channel unit""s interface circuit will eventually allow the counter to roll over subsequent to the last NMQ transition, so that the counter will clock the output flip-flop, whereby the output gate changes the NMP output lead, terminating the pseudo NMP signal. The enable lead is then de-asserted, so that the output of the input gate will no longer follow changes in state of the NMQ lead, and therefore will not repeatedly clear the counter and the output flip-flop. As a result, the output gate will maintain the NMP output lead de-asserted.